This invention relates to an information processor having low cost and capable of improving the operating speed of a central processing unit (CPU).
In recent years, the density of integrated circuits for fabricating a memory element has been increased greatly.
Taking a main memory element as an example, although the access time and the cycle time have not been changed substantially, the memory capacity per one chip has been increased to about 4 to 16 times of those of the prior art. Further, the memory capacity of a scratch pad memory device (SPM) having fast access time in which read/write and arithmetic operations can be performed in the fundamental cycle time of the CPU has been increased to 16 words.
Considering system cost, the percentage cost of the software of a computer system has also been increased in recent years. For this reason, it becomes important to use software prepared for use in conventional computers in a new type of computer without any modification.
Assume now that the number of bits that constitute a register of a prior art computer and of the word length of a data processed by an arithmetic logic unit (ALU) is 16 bits and that the processing unit of an instruction and an operand are also 16 bits, in a new type computer constructed to execute also a plurality of programs already prepared for use in the prior art computer, it can readily be understood by one skilled in the art that the number of bits comprising the registers in the new computer should also be 16.
On the contrary, for the purpose of improving the performance of a computer, it is essential to use high speed elements (for example, a Shotkey TTL, emitter coupled logic (ECL), etc.) and to increase, as far as possible, paralellism of the processing. For example, in order to obtain a main memory data transfer rate exceeding a specific rate, it is necessary to read/write the main memory device with 32 bit units instead of 16 bit units.